UNIVERSITY OF HERTFORDSHIRE
		 COMPUTER SCIENCE RESEARCH COLLOQUIUM


                           "Delayed Branches"


                              Colin Egan 
                      (School of Computer Science,
                      University of Hertfordshire)

        	       11 January 2006 (Wednesday) 

                          Lecture Theatre E350
		       Hatfield, College Lane Campus
			       3 - 4 pm

       	       Coffee/tea and biscuits will be available.
			 [Catering Permitting]

		    Everyone is Welcome to Attend
			  [Space Permitting]



Abstract:

Improvement in processor processing performance is a major 
consideration for Computer Architecture designers. A means of achieving 
this in modern processors is by pipelining and multiple instruction issue 
(MII). An essential feature of processor performance of a pipelined machine 
is ensuring the steady flow of instructions into the initial stages of the 
pipeline. However there are several detrimental factors reducing the upper 
bound of processor performance: control hazards, data dependencies, memory 
bandwidth and structural hazards.

This study concerns the impact of control hazards and true 
data-dependencies. Control hazards, such as branch instructions, interrupt 
the flow of instructions in the pipeline. As the issue rate increases with 
MII, the penalty associated with control hazards increases significantly 
impeding the gain on processor performance. The impact of control hazards 
can be reduced through instruction scheduling, branch prediction strategies 
or a combination of both. Data dependencies are a major constraint on 
instruction scheduling and are categorised into: true dependencies, 
anti-dependencies and output dependencies. True data-dependencies are the 
ultimate limitation of instruction level parallelism (ILP), since anti- and 
output-dependencies can be removed by register renaming.

In this study the impact of control hazards is reduced statically, by 
filling branch delay slots with meaningful code. We show that over 90% of 
delay slots in the delay region can be filled with independent instructions 
and we achieve a 3 fold increase in speed-up over a baseline model.

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Hertfordshire Computer Science Research Colloquium
http://homepages.feis.herts.ac.uk/~nehaniv/colloq