UNIVERSITY OF HERTFORDSHIRE
             COMPUTER SCIENCE RESEARCH COLLOQUIUM

                            presents

     "Making MPSoCs Time-Predictable -- A Preplanning Approach"

                     Prof. Peter Puschner
            (Vienna University of Technology, Austria)
                    12 December 2013 (** Thursday ***)
                          1 pm -2 pm

                  Hatfield, College Lane Campus
                   *** Seminar Room F321 ***

                  Everyone is Welcome to Attend

                  Refreshments will be available


Abstract:


Multi-core processors promise a number of benefits for dependable embedded
systems. They offer higher performance than single-core processors
and consume less energy than high-speed single cores of equivalent
computational power, thus reducing the number of computational nodes
and wiring in a system and increasing robustness. Further, the cores
of heterogeneous multi-cores can be tailored to match the specific
functionalities of the embedded computer system. Despite these promises,
multi-cores are not automatically well-suited for safety-critical and
mixed-criticality embedded systems - if not carefully designed, the lack
of spatial and temporal partitioning and the barely analysable worst-case
timing behaviour of performance-enhancing features render the validation
of claims about the dependability and correct timing of applications on
today's powerful multi-cores impossible.  This talk presents some key
principles that must be followed when constructing the architecture and
writing the software for embedded multi-core systems if those systems are
to be used in safety-critical or mixed-criticality real-time applications.

About the Speaker:

Prof. Peter Puschner is is a professor in computer science at Vienna
University of Technology and his main research interest is on hard
real-time systems for safety-critical applications, with a focus on the
worst-case execution time (WCET) analysis and software/hardware
architectures for time- predictable computing systems. He has published
more than 100 refereed conference and journal papers, received one patent,
and was a guest editor of two special jounal issues on WCET analysis
(Real-Time Systems Journal, Kluwer, 2000; Journal of Systems Architecture,
Elsevier, 2011). P. Puschner chaired the PC of ISORC 2003 and ECRTS 2004,
was the general chair of the Euromicro Conference on Real-Time Systems
2002, ISORC 2004, and SEUS 2010, and was the local chair of the IEEE
Real-Time Systems Symposium in 2011. He is in charge of the steering
committees of the workshop series on worst-case execution-time analysis
(WCET) and the International Workshop on Software Technologies for Future
Embedded and Ubiquitous Computing Systems (SEUS).
Prof. Puschner received a Marie-Curie Category-30 fellowship and spent one
year (2000) as a visiting researcher at the University of York, England.
He was the local scientific coordinator in a number of research projects
and networks of excellence funded by the European Commission (SETTA;
CaberNet, Artist2, ArtistDesign) and currently leads the TUV group in the
EC FP7 project T-CREST. Further, he was the principal investigator of the
projects MoDECS (model driven design of distributed embedded computer
systems) and TeDES (automatic test case generation for safety-critical
applications) funded by the Austrian Ministry of Research, Innovation, and
Technology. He is a member of the IEEE Computer Society, IFIP working
group 10.2 on Embedded Systems, Euromicro, the OCG (Austrian Computer
Society), and the Marie-Curie Fellowship Association.





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Hertfordshire Computer Science Research Colloquium
http://cs-colloq.stca.herts.ac.uk